1. Technical Field
The present invention relates to a method of manufacturing a printed circuit board.
2. Description of the Related Art
With the development of the electronics industry, there has been a growing demand for smaller electronic parts and more advanced functions. Such a trend requires that circuit patterns be implemented in higher densities in the printed circuit board, and accordingly various methods of forming fine circuit patterns have been developed.
For example, a conventional structure, in which circuit patterns are formed on the surfaces of an insulator, can create several problems when it is applied to a high density circuit (e.g. 20/20 μm or less), and thus a structure has been proposed as an alternative, in which the circuit patterns are buried inside the insulator. To implement this structure, a method of forming circuits has been developed that includes forming a circuit pattern on a carrier and then pressing the carrier onto the insulator, to transcribe the circuit pattern into the insulator.
However, various problems may occur when using this method. For example, in the operation of processing a via hole using a laser drill, etc., to form a via for interlayer connection, the use of excessive energy can result in holes that deviate from the desired shape. These problems are regarded as obstacles to realizing the structural benefits intended from the structure of buried circuit patterns.
FIG. 1 through FIG. 7 each illustrates a process in a method of manufacturing a printed circuit board according to the related art. In this method, as illustrated in FIG. 1 through FIG. 7, holes 3 can be formed by laser-processing a copper clad laminate, which includes copper foils 2 attached to both sides of an insulator, after which seed layers 4 can be formed by performing electroless copper plating over the inner walls of the holes 3. Then, plating resists 5 can be formed, by applying, exposing, and developing dry films, and circuit patterns 7 can be formed, using electroplating. Afterwards, the plating resists 5 can be removed, and the seed layers 4 and the copper foils 2 can be etched.
This method based on the related art can lead to deviations in thickness after the copper electroplating is performed to form circuit patterns. In addition, the process of etching the seed layers may further increase the deviations in circuit-line thickness and circuit pitch, due to over-etching, etc.